huawei OSN3500 STM-64 E1/T1 next-generation optical transmission equipment SDH
Short Description:
| Subrack dimensions | 722 mm (H) x 497 mm (W) x 295 mm (D) |
| Switching capacity | Packet: 100 Gbit/s. TDM: 200 Gbit/s (high order), 20 Gbit/s (low order) |
| Service slots | 15 slots for processing boards and 16 slots for interface boards |
| Highly reliable design | 1+1 hot backup for power supply modules1+1 hot backup for system control boards1+1 hot backup for cross-connect and synchronous timing boardsRedundancy protection for fan modules |
| Supported interfaces | |
| Packet transport interfaces | E1, STM-1, FE/GE/10GE |
| MSTP interfaces | STM-64/16/4/1, E1/E3/E4/T1/T3, FE/GE/10GE, DDN, IMA/ATM, SAN |
| WDM interfaces | 40-channel DWDM interfaces, compliant with ITU-T G.694.18-channel CWDM interfaces, compliant with ITU-T G.694.2 |
| Power Supply | –72 to –38.4V DC; 110/220V AC (External module) |
| Operation Environment | Temperature Relative HumidityLong term: 0°C to 45°C 10% to 90%Short term: –5°C to 55°C 5% to 95% |
| Service features | E-Line and E-LANQinQMPLS-TP based VPWS and VPLSTDM PWE3: CESoPSN and SAToP, compression of idle timeslotsETH PWE3IGMP SNOOPING V2BlacklistBroadcast packet suppressionACL |
| QoS features | H-QoS scheduling and traffic shapingDiffServ mode based on traffic classificationSimple traffic classification, complex traffic classification, per hop behavior (PHB), and ACLCommitted access rate (CAR)PQ scheduling priority, weighted fair queuing (WFQ), and PQ+WFQ queuingTail drop and weighted random early detection (WRED)Eight priority queuesShaping based on port scheduling priority |
| Hardware-based OAM | |
| MPLS OAM | Supports both LSP OAM and PW OAM:CV (Connectivity Verification)FFD (Fast Failure Detection)FDI (Forward Defect Indicator)BDI (Backward Defect Indicator)CES PW VCCVPingTraceroute |
| Ethernet OAM | ETH-CC (continuity check), ETH-loopback, ETH-link traceRemote loopback, remote fault detection |
| Carrier-class protection | 1+1 and 1:1 Linear MSP, guaranteeing 50 ms switching time1+1 and 1:1 protection for label switched path (LSP) and pseudo-wire (PW), guaranteeing 50 ms switching timeMulti-section pseudo-wire (MS-PW)Link aggregation group (LAG) protectionMulti-chassis link aggregation group (MC-LAG) protectionDual-homing protectionLPTSTP/RSTP/MSTP |
| Clock synchronization | Two external clock inputs/outputs (2 MHz or 2 Mbit/s)Two external time signals (1 pps+TOD)Adaptive clock recovery (ACR)Synchronous EthernetIEEE 1588v2 |
| Interface | Electrical interfaces: DDN (V.35/V.24/X.21/RS-449/RS-530/RS-530A), E1/T1, E3/T3, E4, STM-1(E), 10/100BASE-TX, 1000BASE-TOptical interfaces:- Ethernet 100base-FX, 1000BASE-SX/LX/ZX, 10GBASE-LR/LW- STM-1 S-1.1, L-1.1, L-1.2 - STM-4 S-4.1, L-4.1, L-4.2- STM-16 I-16, S-16.1, L-16.1, L-16.2, V-16.2, U-16.2 - STM-64 I-64.2, S-64.2, L-64.2b, P1L1-2D2, V-64.2- 40-channel DWDM interfaces (FEC off band), compliant with ITU-T G.694.1- 8-channel CWDM interfaces, compliant with ITU-T G.694.2- Others: FC/ESCON/DVB-ASI |
| Carrier-class protection | Mesh Protection and restoration (ASON)-Distributed restorable rerouting protection-Five dedicated protection scheme levels based on different SLA: Diamond, Gold, Silver, Copper and IronSDH Network Protection2/4 fiber MS-SP Ring, 1+1 or 1:n (n<=14) linear MSP, SNCP/SNCMP/SNCTP;, fiber shared virtual path protection, fiber shared MS-SP Ring (one optical interface can support 2 groups of MS-SP Rings), DNI (ITU-T G.842)Service ProtectionEthernet: RPR, ERPS, RSTP, LAG/DLAG/PPS/BPSATM: VP-RING, PPS/BPSElectrical Interface Protection1:n tributary protection for E1/T1, E3/T3, E4, STM-1(e), and FE |
| Multi-service Transport Features | Ethernet Over SDH- GFP/LAPS/VCAT/LCAS- L2 switch, 64 aggregation directions for powerful Ethernet convergence- Mapping granularity, VC-12-nv/VC-3-nv, and VC-4-nv- Point-to-point LPT, point-to-multi-point LPT- MPLS and stackable VLAN for L2 VPN - 4/8-level CoS, CAR based on 64K granularity- IEEE 802.3ah, 802.1agRPR- Automatic topology discovery- 3-level CoS, A (A0/A1) / B (B-CIR/B-EIR) / C- Steering/Wrapping/Steering + Wrapping protection scheme guarantee 50ms switching- Spatial reuse of bandwidth with fairness algorithm- Integrated MPLS with RPR to provide VLL/VPLS serviceATM- Support 2M, 34M, 155M, 622M ATM, and IMA E1- Support up to 93 IMA group and 189 E1sOthers- Support FC/ESCON/DVB-ASI- Support DDN (Nx64K) and framed E1 |
| Clock synchronization | Two external clock inputs/outputs (2 MHz or 2 Mbit/s)Two external time signals (1pps+TOD)Line clock sourceTributary clock sourceIEEE 1588v2 |
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